Espressif Systems /ESP32-C2 /SPI1 /USER

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Interpret as USER

Description

SPI1 user register.

Fields

CK_OUT_EDGE	the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.
FWRITE_DUAL	In the write operations read-data phase apply 2 signals
FWRITE_QUAD	In the write operations read-data phase apply 4 signals
FWRITE_DIO	In the write operations address phase and read-data phase apply 2 signals.
FWRITE_QIO	In the write operations address phase and read-data phase apply 4 signals.
USR_MISO_HIGHPART	read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.
USR_MOSI_HIGHPART	write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.
USR_DUMMY_IDLE	SPI clock is disable in dummy phase when the bit is enable.
USR_MOSI	This bit enable the write-data phase of an operation.
USR_MISO	This bit enable the read-data phase of an operation.
USR_DUMMY	This bit enable the dummy phase of an operation.
USR_ADDR	This bit enable the address phase of an operation.
USR_COMMAND	This bit enable the command phase of an operation.

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